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Spirent KB Article
Doc ID: FAQ19669
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MARTS, BRTU: What causes HDLC Clock Glitch errors?
Environment/Versions
MARTS - All Versions
BRTU - All Versions
Answer
The error is caused by either:
Issue with the HDLC bus between master and expansion shelves.
Bad or incorrect external clock source on the master or expansion shelves.
Bad or incorrect Power Supply Unit on the master or expansion shelves.
Version
1.0
Publish Date
2021-07-01
Categories
Product : REACT
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